The present invention relates to processor clock circuits, and more particularly, to a method and apparatus for limiting a processor clock frequency.
Processor manufacturers perform various tests to rate each processor for a particular clock frequency. Tests are typically performed at the wafer level, and also at the chip level. More restrictive tests can also be performed at the card level by subjecting the processor to the constraints of memory and other devices. Based on these tests, the manufacturer can determine the maximum clock speed at which the processor can operate without errors. However, many electronics manufacturers are very conservative in their clock ratings. For example, a processor that successfully operates during tests at 166 MHz may be rated at only 120 MHz.
Moreover, there is a demand for processors across a wide variety of clock frequencies. As a result, manufacturers typically intentionally rate processors at frequencies that are significantly lower than the processor""s maximum clock frequency to meet demand for processors at a particular frequency. For example, even though 80% of a manufacturer""s processors may operate correctly at 300 MHz, many of these processors will be marked and sold by manufacturers as slower processors (e.g., 133, 150, 166, 200 and 250 MHz) due to market demand for processors across a wide variety of clock frequencies.
Because most processors can be clocked at frequencies significantly greater than their rated (marked) clock frequency, there is presently a problem with resellers and distributors remarking processors with a higher frequency and then selling the processors as the higher speed part to charge a higher price. This is possible because the processor clock speed is typically initialized from the motherboard at reset. One or more jumpers on the motherboard can be set to select a processor clock frequency. At system reset, the motherboard outputs frequency selecting control signals to the processor to select a processor clock frequency. At reset, the processor samples these frequency selecting control signals. The clock generation logic in the processor then performs the appropriate frequency multiplication and division on the external clock signal provided from the motherboard to generate the selected processor clock frequency. This allows unscrupulous processor resellers to purchase less expensive processors that are rated at lower clock frequencies and then remark the processors to a higher clock frequency. This also allows personal computer manufacturers to overclock these processors (operate the processor at a clock frequency greater than the originally rated frequency) once they are installed in personal computers.
There have been attempts to solve the overclocking problem. According to one approach, a maximum processor clock frequency is selected by tying several processor input pins high or low using pull-up and pull-down resistors. However, this hardwiring approach to setting a maximum clock frequency is susceptible to external manipulation by users and resellers. A user can reconnect these processor input pins to high or low to select a different clock frequency. As a result, this hardwiring approach is not secure. Moreover, the hardwiring approach is inflexible and cumbersome for processor manufacturers because the maximum clock frequency can be adjusted only by resoldering the pull-up and pull-down resistors. A more flexible approach is desirable.
Therefore, a need exists for a more secure mechanism that prevents resellers and users from operating the processors at clock frequencies that are greater than their rated clock frequencies, while providing a flexible technique to allow processor manufacturers to more easily adjust the maximum clock frequency.
A method and apparatus is disclosed for limiting a processor clock frequency. The apparatus includes a frequency limiting circuit including one or more programmable fusible elements. The frequency limiting circuit outputs a signal identifying a maximum processor clock frequency based on the state of each of the fusible elements. The apparatus also includes a comparator circuit coupled to the frequency limiting circuit. The comparator circuit receives a signal identifying a selected processor clock frequency as a first input and receives the signal identifying the maximum processor clock frequency as a second input. The comparator circuit outputs a signal indicating whether or not the selected processor clock frequency is greater than the maximum clock frequency.